The invention relates to computer system bus interfaces and particularly to directing address and command information between multiple interfaces on a node in a computer system.
In a multi-CPU system in which multi-CPU nodes are coupled to a pipelined system bus, multiple system bus transactions may be pending at any given time. In addition, each system bus operation may require data movement on a particular node between the system bus and any of the various interfaces on the node. For example, a given node may have multiple CPU and cache subsystems each coupled to its own CPU interface, a block of control and status registers [CSR's] coupled to a CSR interface, and a system bus interface for coupling the node to the system bus. A given system bus operation may require data movement between any of the CPU or CSR interfaces and the system bus interface, between the system bus interface and the system bus, or both. For example, a system bus operation requiring the transfer of data from the cache in one of the CPU and cache subsystems to the system bus would involve data movement between the CPU interface associated with that cache to the system bus interface, and then from the system bus interface to the system bus.
For such a multi-CPU node, some way must be provided for directing address and command information between the system bus and the various interfaces on the node for each outstanding system bus operation, in order that the proper interfaces can initiate the required data transfers to complete the operation. According to one known method, optimum performance is achieved by providing each of a node's interfaces with a dedicated queue of data movement commands containing the commands relevant to the interface. Each interface is termed a "consumer" of the commands provided by its corresponding queue. Each queue's consumer executes the queue commands as fast as possible, stalling only when a data resource is unavailable (i.e. another interface or the system bus is not ready to supply data, or a required data buffer is already in use).
To achieve this, it is known to provide multiple independent queues, one per consumer, with data resource interlock flags. The queue entries consist of data movement commands derived from the address and command portions of outstanding system bus transactions. These data movement commands include copies of all the address and command information required by a consumer to initiate a data transfer. The consumers read these data movement commands from their queues and move data as required in response to the commands. The consumers perform data transfers in parallel to the degree possible as indicated by the interlock flags. However, since such a multi-queue implementation typically requires substantial duplication of information (address, command, etc.) within each queue, it is typically very large; prohibitively so when implemented in design-area sensitive technology.
Alternatively, a single queue feeding multiple consumers can be employed. The single queue implementation requires no duplication of data, making its implementation advantageous in terms of implementation resources--i.e. fewer logic gates are required. Performance, however, is compromised because commands must be executed in the strict order in which they are queued, thus eliminating parallel execution of independent commands.